
IDT / ICS LVDS CLOCK GENERATOR
7
ICS844021BG-01 REV. A OCTOBER 23, 2012
ICS844021-01
FEMTOCLOCKS CRYSTAL-TO-LVDS CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS844021-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS844021-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD and VDDA should
be individually connected to the power supply plane through vias,
and 0.01F bypass capacitors should be used for each pin.
Fig-
ure 1 illustrates this for a generic V
DD pin and also shows that
V
DDA requires that an additional10Ω resistor along with a 10F
bypass capacitor be connected to the V
DDA pin.
FIGURE 1. POWER SUPPLY FILTERING
10
Ω
V
DDA
10
μF
.01
μF
3.3V or 2.5V
.01
μF
V
DD